Multi-queue first-in first-out (FIFO) memory devices may use register files to maintain write flag and read flag counter values for each of a plurality of queues supported by the FIFO memory device. These counter values are typically used as operands when calculating full, almost-full, empty and almost-empty flag conditions on a per queue basis. A conventional multi-port register file may include a plurality of multi-port latch cells (e.g., multi-port SRAM cells). As illustrated by FIG. 1, a conventional multi-port latch cell 10 includes a write port, a pass gate (e.g, CMOS transmission gate), a latch, and first and second read ports. The latch may include a pair of inverters that are connected in antiparallel. The write port is controlled by a pair of differential word lines (shown as UP and UPX), the first read port is controlled by a “read queue” word line RD and the second read port is controlled by a “write queue” word line WR. The latch cell 10 is electrically coupled to three bit lines, shown as DIN, RDOUT and WROUT. The bit lines RDOUT and WROUT are frequently precharged to logic 1 levels (e.g., Vdd) in preparation for each access to a corresponding read port. Based on the illustrated configuration of the latch cell 10, if DIN=0 when the write port is initially accessed, then driving the word line RD to an active high level for short duration will cause the bit line RDOUT to be pulled down to a logic 0 level to reflect a corresponding data value stored within the latch cell. Alternatively, if DIN=1 when the write port is initially accessed, then driving the word line RD to an active high level will not influence the precharged condition of the bit line RDOUT and a logic 1 value will remain at the corresponding read port. The same results also apply to the bit line WROUT when the word line WR is accessed. To prevent contention between the precharge devices (not shown) connected to each bit line RDOUT and WROUT and the pull-down transistors within each latch cell, the word lines RD and WR are not pulsed high when the precharge devices are active.
FIG. 2 illustrates a conventional register file system 20 that may be used in a multi-queue FIFO memory device. The system 20 contains a M×N array of latch cells 10 within a register file 22, where M is a positive integer corresponding to the number of queues supported by the FIFO memory device and N is a positive integer that may equal log2 times a capacity of the FIFO memory device. A bank 24 of address latches receives the word line signals associated with the write port (i.e., UP and UPX) and the word line signals associated with the first and second read ports (i.e., RD and WR). The first clock signal CLK1 is used to synchronize the precharging of the bit lines RDOUT using a first precharge circuit 26a and the second clock signal CLK2 is used to synchronize the precharging of the bit lines WROUT using a second precharge circuit 26b. The first clock signal CLK1 is also used to synchronize the timing of a first bank of latches 28a (e.g., flip-flops (FF)), which are coupled to a first output port OUT1. Similarly, the second clock signal CLK2 is used to synchronize the timing of a second bank of latches 28b (e.g., flip-flops (FF)), which are coupled to a second output port OUT2.
As will be understood by those skilled in the art, the word lines UP and UPX may be activated based on clock signals that are asynchronous relative to the first and second clock signals CLK1 and CLK2. This asynchronous clocking relationship means that new data can be updated into the register file 22 while one or more of the read ports are being accessed and data is being read from the register file 22. This timing overlap may cause incorrect data to be read from the read ports RDOUT and WROUT when the write queue and read queues within the FIFO memory device are the same (i.e., the read word lines RD and WR correspond to the same row as the write word lines UP and UPX). However, even if correct data is read out of the read ports RDOUT and WROUT, sufficient setup times may not be provided before the first and second banks of latches 28a and 28b capture the read data. Such insufficient setup times may result in data and flag generation errors.
Thus, notwithstanding the register file system of FIG. 2, there continues to be a need for improved register file systems that are less susceptible to errors resulting from the asynchronous timing between clock signals associated with the write and read operations within a FIFO memory device.